The present invention relates to a reproducing apparatus, an error correcting device and an error correcting method, and more particularly to those adapted for use in a video tape recorder integrated into a camera where reproduced data is read out from a recording medium, for example, and inputted in two series with regard to one azimuth side and are processed through an error correction circuit.
In the related art VTRs (video tape recorders) known heretofore, there is a type where input data signals composed of video and audio data are recorded in the form of digital signals on a recording medium, such as a magnetic tape. And in such recording, an error correcting code (so called parity bit) generated by an error correction coding process is attached to the data signal so as to correct any error in the video and audio data to be reproduced. In such error correction coding process, it is generally customary to use product codes in many cases.
In a camera-integrated VTR (hereinafter referred to simply as camcorder) where acoustic noise and so forth need to be taken into consideration, the rotation speed of a drum is lowered to reduce such noise, while the number of heads is doubled and the read data are inputted in two series with regard to one azimuth size.
FIG. 8 shows a portable reproducing apparatus 1 consisting of a camcorder or the like, wherein, when data recorded digitally on a recording medium is reproduced therefrom by a plurality of heads so disposed as to correspond respectively to channels A-H for example, the data read out by the heads corresponding to the channels A/E and C/G are inputted in two series. Although the reproducing apparatus 1 is further equipped with heads for the other azimuth side relative to channels B/F and D/H, an explanation will be given below, for the sake of convenience, merely with regard to the one azimuth side composed of channels A/E and C/G.
In the reproducing apparatus 1, reproduced data S1 and S2 supplied via two series of channels A/E and C/G are inputted to a data rate converter 2. Then in converter 2, the reproduced data S1 is stored in a RAM 3 while the reproduced data S2 is stored in a RAM 4. Thus, in the data rate converter 2, rate conversion is executed as the reproduced data, S1 and S2, are stored temporarily in the RAMs 3 and 4 respectively, and are read out therefrom alternately at a rate twice the input rate. Subsequently reproduced data S3 is thus obtained and supplied to an ECC (error correcting code) decoder 5. Then, in the ECC decoder 5, the data S3 is stored in a RAM 6 and the process of error correction is executed while the data S3 is read out. Thereafter the ECC decoder 5 outputs corrected data S4 obtained through the process of error correction executed for the reproduced data S3.
More specifically, since the data is read out from the recording medium by the heads relative to one and the other azimuth sides respectively as shown in FIG. 9, the reproduced data S1 and S2 fed to the data rate converter 2 is inputted to two series of channels A/C and E/G substantially simultaneously in parallel thereto. However, if the reproduced data S1 and S2 inputted in such a state are processed through error correction, there arises a problem that, during the error correction of the data of one channel, the process for the data of the other channel needs to be slowed so that it becomes impossible to execute a real-time process with respect to the input timing.
In the reproducing apparatus 1, the data is read out at double the input rate from the RAMs 3 and 4, and then the reproduced data S1 and S2 are falsely compressed to a reduced data size and are converted into data of a single series through time-division reading by the data rate converter 2. Thereafter, a process of error correction is executed in the ECC decoder 5 to obtain error-corrected data S4.
In the reproducing apparatus 1 of such a configuration, the rotation speed of the drum is lowered to reduce acoustic noise as mentioned, and the number of heads is increased to avoid a decrease of the amount of data read. Since the reproduced data S1 and S2 read out by the heads are thus inputted substantially simultaneously, the reproducing apparatus 1 is so devised that the data rate converter 2 compresses the input data S1 and S2 in individual channels to a reduced data size and reads out the data through time division to thereby convert the data into a single data series.
However, the power required to execute the above process, driving the data rate converter 2 and controlling the accesses to the RAMs 3 and 4 is not small and consequently brings about a problem that the power consumption is increased. Such increase of the power consumption becomes a conspicuous problem particularly in a portable VTR such as a camcorder, and it is difficult to extend the possible driving time.
Although the data rate converter 2 is generally formed into an IC (integrated circuit), the area required for mounting the same is large enough to eventually diminish the area usable for mounting other chip elements and so forth. For this reason, the whole system is rendered dimensionally greater and structurally complicated with a further disadvantage of difficulty in achieving curtailment of the production cost.